The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, lithography has been the traditional method for transferring IC patterns to semiconductor wafers. In a typical lithography process, a resist film is coated on a surface of a wafer and is subsequently exposed and developed to form a resist pattern. The resist pattern is then used for etching the wafer to form an IC. The quality of the resist pattern directly impacts the quality of the final IC. The measures of the quality of a resist pattern include critical dimension variance, line edge roughness (LER), and line width roughness (LWR). As the semiconductor scaling down process continues, it is desirable to improve the existing developing processes and systems so as to reduce critical dimension variance, LER, and LWR of the resist patterns to meet pre-determined critical dimension uniformity (CDU).